1. Field of the Invention
This invention relates to buffer circuits. In particular, the invention relates to dynamically configured buffer circuits.
2. Description of Related Art
Due to the long latency for a Peripheral Component Interconnect (PCI) or PCI-X read request from an inpu/output (I/O) device, a PCI/PCI-X bridge generally treats the inbound read transaction as a delayed transaction in PCI mode or a split transaction in PCI-X mode. A PCI delayed transaction occurs when the I/O device issues an initial read request. When the PCI bridge receives the read completion data, it stores in it in a delayed transaction buffer. When the PCI master returns with the same read request, the read completion data is provided from the delayed transaction buffer. Similarly, a PCI-X split transaction occurs when the I/O device issues an initial read request. Since the PCI-X bridge does not have the read data, it terminates the transaction with a Split Response indicating that the bridge has accepted the read request and will later provide the I/O device with the read completion data. When the bridge receives the read completion data, it stores it in a delayed transaction buffer. The bridge then sends the data to the I/O device as a Split Completion transaction.
A PCI/PCI-X bridge may support multiple concurrent delayed transactions if there are multiple I/O devices or a single I/O device with multiple read requests. In addition, the bus frequency may vary depending on system configurations. The PCI bus can operate at frequencies of 33 MHz or 66 MHz. The PCI-X bus can operate at frequencies of 66 MHz, 100 MHz, or 133 MHz. At these various frequencies, the number of read delayed transactions may be different which affect the depth of the delayed transaction buffer. Existing techniques for buffer management are inefficient. One technique uses a single large content addressable memory (CAM) delayed transaction buffer to support multiple delayed transactions. This technique requires a complex buffer management scheme and is costly. Another technique uses multiple delayed transaction buffers that are deep enough to handle the highest PCI/PCI-X bandwidth and lowest system latency. This technique requires high gate count and wastes hardware when used with lower bus frequencies.
Therefore, there is a need to have an efficient technique to handle multiple delayed transactions for various bus frequencies.